Modern integrated circuits generally comprise a large number of circuit elements. It is desirable to test these circuit elements in order to ensure the proper operation of the integrated circuit. However, the number of test points (that is, locations where signals can be measured) is limited by the number of terminals of the integrated circuit, which are vastly outnumbered by the number of circuit elements to be tested.
Consequently, designers of modern integrated circuits often employ a test technique referred to herein as “scan testing.” FIG. 1 shows a conventional integrated circuit 100 designed to permit scan testing. According to this technique, integrated circuit 100 includes a number of storage elements 102 that can be loaded with a test vector. The test vector is a binary number that includes bits to be loaded into storage elements 102. Each storage element 102 comprises a flip-flop 118 and a switching unit such as a multiplexer 116. Each multiplexer 116 is controlled by a scan shift signal 104. When scan shift signal 104 is negated (for example, during normal operations), each multiplexer 116 gates signals from circuits such as optional logic circuits 120 to the flip-flop 118 in its storage element 102. However, when scan shift signal 104 is asserted (for example, during scan testing), each multiplexer 116 gates signals from another storage element 102 to the flip-flop 118 in its storage element 102, thereby causing the storage elements 102 to interconnect serially, forming a “scan chain.”
During scan test, scan shift signal 104 is asserted, thereby forming the scan chain. Then the test vector (also referred to as “scan data”) is shifted into the scan chain as scan data in signal 106 through the first storage element 102aa in the scan chain. Scan shift signal 104 is then negated, breaking the scan chain and restoring normal operational connections to storage elements 102. A clock driver 114 then toggles the clock signals 108 of the integrated circuit one or more times to simulate actual operation. Scan shift signal 104 is then asserted again, forming the scan chain again. Then the data in the storage elements 102 are then shifted out of the scan chain as scan data out signal 110 through the last storage element 102bn in the scan chain, and compared to a predetermined result vector to obtain a test result.
Many modern integrated circuits employ multiple clock signals, referred to herein as “domain clock signals” 108. The circuit elements driven by one clock signal 108 define a “clock domain” 112. Owing to design constraints (for example, when there is a lack of scan pins for scan chains in the design), it is often necessary to include multiple clock domains within a single scan chain. Referring to FIG. 1, clock domain 112a comprises storage elements 102aa through 102an, which are driven by domain clock signal 108a; and clock domain 112b comprises storage elements 102ba through 102bn, which are driven by domain clock signal 108b. 
Within each clock domain 112, it is necessary to ensure that the clock signal 108 reaches each of the clocked circuit elements at substantially the same time. In addition, clock driver 114 can directly drive only a few circuit elements. The number of circuit elements a clock driver can drive is referred to as the clock driver's “fan-out.” The number of circuit elements in a clock domain 112 that must be clocked by clock driver 114 generally far exceeds the fan-out of clock driver 114. To solve both of these problems, designers employ a number of delay elements between the clock driver and the clocked circuit elements. The collection of interconnected delay elements is referred to as a “clock tree.” The process of determining the number and location of the delay elements for a clock domain 112 is referred to as generating a “clock tree” for the clock domain 112.
When generating a clock tree for a clock domain 112, a designer generally chooses the smallest number of delay elements that provide a common clock delay for each of the clocked circuit elements in the clock domain 112. As a result, the total clock delays usually differ for different clock domains 112. While this is not a problem during normal operation, it causes timing problems during scan test. One common solution is to isolate clock domains from each other by inserting a latch, referred to as a “lockup latch,” between storage elements 102 that are connected in the scan chain but belong to different clock domains 112. Referring again to FIG. 1, a lockup latch (LUL) 122 is connected between storage elements 102an and 102ba, thereby isolating clock domains 112a and 112b from each other.
One disadvantage of this approach is that the designer must correctly identify the locations where lockup latches are needed. Much of the layout process for modern integrated circuits is automated using software layout tools. However, even these sophisticated layout tools occasionally fail to insert lockup latches where needed, resulting in lost design and test time. This problem is exacerbated when more than two clock domains (and therefore more than one lock-up latch) are present in the scan chain.